FIG. 1 is a schematic functional block diagram illustrating the architecture of a conventional DDR memory system. As shown in FIG. 1, the DDR memory system 100 comprises an application-specific integrated circuit (ASIC) 110 and a DDR memory 120.
The ASIC 110 comprises a memory controller 112 and a physical layer (PHY) circuit 114. The PHY circuit 114 of the ASIC 110 and the DDR memory 120 exchange various signals through a memory bus 122. A DDR PHY Interface 116, which is also referred as a DFI interface, is connected between the memory controller 112 and the PHY circuit 114. That is, plural signals are transmitted between the memory controller 112 and the PHY circuit 114 through the DFI interface 116.
The ASIC 110 further comprises a phase-locked loop (PLL) 118. The PLL 118 generates a DFI clock (DFIclk) to the memory controller 112 and the PHY circuit 114. Consequently, the memory controller 112 and the PHY circuit 114 are operated in the same DFI clock domain.
The PHY circuit 114 further comprises a data physical layer circuit (Data0 PHY) 131, a data physical layer circuit (Data1 PHY) 132 and a command physical layer circuit (CMD PHY) circuit 133. Of course, the PHY circuit 114 of the ASIC 110 may comprise more than two data physical layer circuits. As the data amount increases, the number of the data physical layer circuit increases.
When the memory controller 112 intends to store a write data into the DDR memory 120, the memory controller 112 generates a write command and the write data. The write command is transmitted from the memory controller 112 to the CMD PHY circuit 133 through the DFI interface 116. In addition, the write command is transmitted from the CMD PHY circuit 133 to the DDR memory 120 through the memory bus 122. The write data is transmitted from the memory controller 112 to the two data physical layers 131 and 132 through the DFI interface 116. In addition, the write data is transmitted from the two data physical layers 131 and 132 to the DDR memory 120 through the memory bus 122. Consequently, the write data is stored into the DDR memory 120 according to the write command.
When the memory controller 112 intends to acquire a read data from the DDR memory 120, the memory controller 112 generates a read command. The read command is transmitted from the memory controller 112 to the CMD PHY circuit 133 through the DFI interface 116. In addition, the read command is transmitted from the CMD PHY circuit 133 to the DDR memory 120 through the memory bus 122. Moreover, the DDR memory 120 generates the read data according to the read command. The read data is transmitted from the DDR memory 120 to the two data physical layers 131 and 132 through the memory bus 122. In addition, the read data is transmitted from the two data physical layers 131 and 132 to the memory controller 112 through the DFI interface 116.
As mentioned above, the CMD PHY circuit 133 transfers the command in one direction, and the two data physical layers 131 and 132 transfer data in two directions.
According to the specifications of the DDR memory 120, the write command and the write data are transferred according to a specified timing sequence relationship. After the memory controller 112 transfers the write command and the write data to the PHY circuit 114 according to a specified timing sequence relationship, the PHY circuit 114 transfers the write command and the write data to the DDR memory 120 according to the specified timing sequence relationship. Similarly, the read command and the read data are transferred according to the specified timing sequence relationship.
The memory controller 112, the PHY circuit 114 and the DFI interface 116 in the ASIC 110 are operated to transfer various signals according to the DFI clock (DFIclk). Consequently, the DDR memory controller 112 and PHY circuit 114 have to perform the clock tree balance from a DFI clock tree root.
In practice, the CMD PHY circuit 133 and the data physical layers 131 and 132 are allocated at different positions of the ASIC 110. In other words, it is almost impossible to design the suitable DFI clock tree root.
Consequently, after the memory controller 112 transfers the write command and the write data according to the specified timing sequence relationship, the write command and the write data received by the PHY circuit 114 are not maintained according to the specified timing sequence relationship. Consequently, the write data or the read data is possibly lost or the DDR memory 120 is erroneously operated.